///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//File Name: Multiplication_tb_python.v
//Created By: Sheetal Swaroop Burada
//Date: 30-04-2019
//Project Name: Design of 32 Bit Floating Point ALU Based on Standard IEEE-754 in Verilog and its implementation on FPGA.
//University: Dayalbagh Educational Institute
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

`define N_TESTS 65536
//`define N_TESTS 100000

module add_tb;

	reg clk = 0;
	reg rst_n = 0;
	reg [31:0] a_operand;
	reg [31:0] b_operand;
  reg        op_en;
	reg        rd_file;
	
	wire Exception,Overflow,Underflow;
	wire [31:0] result;
	wire valid;

	reg [31:0] Expected_result;

	reg [95:0] testVector [`N_TESTS-1:0];

	reg test_stop_enable;

	integer mcd;
	integer test_n = 0;
	integer pass   = 0;
	integer error  = 0;

	float_adder DUT(
			.clk(clk),
			.rstn(rst_n),
      .fp_adder__op1(a_operand),
      .fp_adder__op2(b_operand),
      .fp_adder__op_en(op_en),
      .fp_adder__res(result),
      .fp_adder__vld(valid),
      .fp_adder__is_nan(),
      .fp_adder__is_inf()
    );

	always #5 clk = ~clk;

	initial
	begin
		rst_n = 0;
		#20
		rst_n = 1;
	end

	initial  
	begin 
		rd_file = 0;
    $fsdbDumpfile("test.fsdb");
		$fsdbDumpvars("+all");
		//$readmemh("TestVectorMultiply", testVector);
		$readmemh("./add_reference", testVector);
		mcd = $fopen("Results_add.txt");
		#10
		rd_file = 1;
	end 

	always @(posedge clk or negedge rst_n)  
	begin
			if(~rst_n) begin
				pass <= 0;
				test_n <=  0;
				error <= 0;
				op_en <= 0;
				test_stop_enable <= 1'b0;
			end
			else if(rd_file==1) begin
				{a_operand,b_operand,Expected_result} <= testVector[test_n];
				test_n <= test_n + 1'b1;
				op_en <= 1;
				if ((result == Expected_result))
					begin
						$fdisplay (mcd,"TestPassed Test Number -> %d",test_n);
						pass <= pass + 1'b1;
					end
					/*
				else if (result^Expected_result == 1)
					begin
						$fdisplay (mcd,"TestPassed Test Number -> %d",test_n);
						pass = pass + 1'b1;
					end
					*/
				else
					begin
						$fdisplay (mcd,"Test Failed, Adder_A: %h, Adder_B: %h, Expected Result = %h, Obtained result = %h, Test Number -> %d",a_operand, b_operand, Expected_result,result,test_n);
						error = error + 1'b1;
					end
				
				if (test_n >= `N_TESTS) 
				begin
					$fdisplay(mcd,"Completed %d tests, %d passes and %d fails.", test_n, pass, error);
					test_stop_enable <= 1'b1;
				end
			end
	end

always @(posedge test_stop_enable)
begin
$fclose(mcd);
$finish;
end

endmodule
